As is well known, a pulse signal is a signal which comprises alternating high and low level portions, and is widely used as a signal for controlling various actuators. More specifically, a pulse signal may be used for, for example, controlling automobile engine fuel injection, engine ignition timing, a motor chopper, etc.
FIG. 1 is a block diagram of an example of a prior art pulse generator circuit which was invented by the inventor and is disclosed in Japanese Published Patent Application No. HEI 1-73812 (corresponding to U.S. Pat. No. 4,805,199). This pulse generator circuit is incorporated in a one-chip microcomputer which is primarily to execute real-time processing.
Referring to FIG. 1, a CPU 1 of a microcomputer is connected through a data bus 2 to a prescaler 9, a counter buffer 15, an output level storage circuit 10, a counter 12, and other circuits for transferring various data signals therebetween.
A count start value is set in the counter 12 as a reload value. When the count of the counter 12 underflows, the counter 12 produces an underflow signal. The underflow signal is applied as a control signal to a gate 14 through a line 13a, and is also applied through a line 13b to the output level storage circuit 10 as a clock pulse therefor. The underflow signal is also applied to the CPU 1.
The counter 12 is coupled via the gate 14 to the counter buffer 15. When the gate 14 is enabled in response to the underflow signal applied thereto through the line 13a, a value stored in the counter buffer 15 is set in the counter 12 as a reload value.
A clock signal generator circuit 8 generates a clock signal (internal clock) with which the microcomputer system operation is referenced. The clock signal is applied to the prescaler 9.
The prescaler 9 is a frequency divider circuit, which frequency-divides a reference clock signal applied to it from the clock signal generator circuit 8 to produce a count clock signal of a frequency required by the counter 12. This count clock signal is applied via a count-enable switch 16 to the counter 12.
The output level storage circuit 10 shown in FIG. 1 comprises a looped four-stage shift register arrangement including four stages Q0 through Q3. Data, i.e. "1" or "0", corresponding to levels in a pulse signal to be developed from the microcomputer system, has been pre-set in the respective stages of the output level storage circuit 10 by the CPU 1. The value stored in the stage Q3 of the output level storage circuit 10 is applied to an output terminal 11 of the microcomputer system, and each time the underflow signal is applied from the counter 12 to the output level storage circuit 10, the contents of the respective stages Q0-Q3 are shifted rightward in a circulating manner so that the respective contents of the stages are successively provided from the stage Q3 to the output terminal 11.
Now, the operation of the above-described prior art pulse generator circuit is described with reference to a timing chart shown in FIGS. 2(a)-2(c).
Let it be assumed that "0", "1", "0", and "0" are initially set in the shift register stages Q0, Q2, Q3, and Q4, respectively, of the output level storage circuit 10 and that the value "0" held in the stage Q3 is developed as an output at the output terminal 11. Since the output appearing at the output terminal 11 is the value "0" held in the stage Q3, the level of the output pulse signal is low as shown in FIG. 2(a).
Let it be assumed again that under this condition, as shown in FIG. 2(b), the CPU 1 sets a count start value N1, as an initial value, in the counter 12 and a reload value N2 in the counter buffer 15, respectively, through the data bus 2 at a time T21.
At a time T22, count-enable switch 16 is closed, and the content of the stage Q2 of the output level storage circuit 10 is shifted to the register stage Q3 from Q2 in response to a count clock pulse applied thereto from the prescaler 9. Since the value now shifted to the stage Q3 from the stage Q2 is also "0", the output pulse from the output terminal 11 remains at the low level as shown in FIG. 2(a). At the same time, the counter 12 starts counting the clock pulses provided by the prescaler 9. More specifically, the counter 12 decrements one count for each clock pulse from the count start value N1 held in the counter 12, and, TN1 after, at a time T23, underflow occurs and an underflow signal is developed. The time period TN1 corresponds to the count N1 in the counter 12. The underflow signal is applied to the output level storage circuit 10, so that the shifting operation takes place in the circuit 10 and the value in the output stage Q3 is now the value "1" originally set in the stage Q1, which now developed at the output terminal 11. Thus, the level of the output pulse signal changes to a high level as shown in FIG. 2(a).
At the same time, the underflow signal is also applied via the line 13a to enable the gate 14 so that a new reload value N2 is loaded into the counter 12 from the counter buffer 15. Then, the counter 12 resumes counting from the new count start value N2.
At a time T24, TN2 after the T23, where TN2 corresponds to the count N2 in the counter 12, the counter 12 underflows again, so that, as in the previous case, the value in the output stage Q3 of the output level storage circuit 10 changes from "1" originally set in the stage Q1 to "0" which was originally set in the stage Q0. Thus, the value "0" is now developed at the output terminal 11. Thus, the output pulse signal changes to the low level.
Thus, a pulse signal, as shown in FIG. 2(a), having a pulse width (T23-T24) corresponding to the initial count preset in the counter 12 is generated.
The above-described conventional pulse generator circuit with the described arrangement and operation has problems, which are now discussed hereinafter.
For example, in air/fuel ratio control, which is one of automobile engine fuel injection controlling techniques, it is necessary to supply fuel to a combustion chamber of an engine in an amount matching the amount of air taken into the chamber during one intake stroke. In such air/fuel ratio control, the amount of fuel supplied is determined by the time when a fuel injector is turned on. For such engine air/fuel ratio control, a micro-computer system including a pulse generator circuit such as one stated above is frequently used to provide a pulse signal necessary for controlling the amount of fuel to be supplied.
When an automobile is running, the intake amount of air and the engine rotation speed vary from time to time depending on the operating state of an accelerator, road conditions, etc., and, therefore, it is desirable to adjust the amount of fuel to be injected even after the fuel injection based on the data corresponding to the intake amount of air, the engine rotation speed, the state of the accelerator, etc. measured just prior to the fuel injection is started.
A timing chart for use in explaining the adjustment of the amount of injected fuel by means of the conventional pulse generator circuit is shown in FIGS. 3(a)-3(d).
A crank angle sensor signal shown in FIG. 3(a) is a signal indicative of an engine crank angle. One period of the crank angle sensor signal corresponds to one rotation cycle of the engine. Thus, the engine rotation speed can be known by counting the number of periods of the crank angle sensor signal. This signal is used also as a reference signal for measuring the intake amount of air and also for determining the time when fuel is to be injected.
When the crank angle sensor signal is provided, the engine rotation speed, the intake amount of air taken into the combustion chamber, etc. are immediately measured in order to determine the amount of fuel to be injected.
FIGS. 3(a) to 3(d) is now explained with an assumption that, as in FIGS. 1 and 2(a)-2(c), "0", "1", "0", "0" are originally set in the register stages Q0, Q1, Q2, and Q3, respectively, which is shown in FIG. 3(d).
At a time T31, a value N1 providing an optimum fuel injection starting timing is set in the counter 12 of the pulse generator circuit, as shown in FIG. 3(c), and an initial value N2 providing a pulse width TN2 corresponding to the determined amount of fuel to be injected is set in the counter buffer 15. Then, the count-enable switch 16 is closed at a time T32.
After the closure of the count-enable switch 16 at the time T32, the first count-down operation is started from the initial count value N1, and underflow occurs at a time T33. During the first count-down operation, the level of the output pulse signal at the output terminal 11 is low, as shown in FIG. 3(b), and, therefore, fuel is not injected.
Then, at the time T33, the second count-down cycle starts from the initial count N2 which corresponds to a time interval during which fuel is injected. During the second count-down operation, the level of the output pulse signal at the output terminal 11 is high, and fuel is injected or supplied to the engine. Now, let it be assumed that at a time T34 which is before the time T36 at which the second count-down operation or fuel injection would end, the engine rotation speed changes or the amount of stepping on the accelerator pedal changes. When such a change occurs, the count in the counter 12 must be corrected by .alpha. in order to change the amount of fuel to be injected. For this correction, the CPU 1 must read out the count n in the counter 12 at the time T34 during the second count-down cycle, add the value .alpha. to the read out count n, and write in the counter 12 the value n+.alpha. minus a count .beta. which corresponds to a processing time TS (hereinafter referred to as software processing time) necessary for making the correction in accordance with a program (software). The writing of the new count into the counter 12 is carried out at a time T35 which is the time TS after the time T34. As a result, the time period during which fuel is injected or, in other words, during which the output pulse signal of the pulse generator circuit is maintained at the high level is extended from the initially set time period TN2, corresponding to the count N2, by a time period T.alpha. corresponding to the added count value .alpha. in the counter 12.
Thus, in the conventional system, various restrictions are added when software is prepared. For example, the software processing time TS must be constant, any interruptions must be inhibited during a time period when correction is being carried out, etc. Furthermore, the conventional system involves restrictions on control. For example, because the entire processing is delayed by the time TS necessary for software processing, the correction is possible only before the time point T37 which, in turn, is earlier by TS than the termination of the fuel injection.
The object of the present invention is to eliminate various restrictions such as the ones stated above, by providing a pulse generator circuit in which correction of a pulse width while a pulse signal is being generated is not affected by a delay which would be caused due to software processing and, therefore, the pulse width can be changes as desired at any desired time.